Vera · GB10 · Grace — three different positions inside the same company's CPU portfolio. We line up the official specs and we are honest about why an apples-to-apples comparison with AMD and Intel does not cleanly fall out.
"NVIDIA announced a CPU too" is a sentence that, depending on when you say it, points at one of three different chips. As of May 2026 the lineup looks like this — the GB10 Superchip that you can already buy on your desk inside DGX Spark (released 2025-10-15) [2]; the Grace Superchip that has been carrying a generation of the data-center line [3]; and the next-gen Vera CPU, paired with the Rubin GPU and announced as Vera Rubin NVL72 with a 2H 2026 launch [4]. Three chips, three positions, three sets of customers.
This piece cites only verified primary or trusted secondary sources — four of them: NVIDIA official, MediaTek's official press release, ServeTheHome, and Tom's Hardware. Pricing, several process / clock / TDP details, and most importantly the head-to-head per-benchmark comparison against AMD/Intel current parts are not covered inside that verified set. We mark each such gap as "not confirmed" rather than fill it with guesses.
The chip a reader is most likely to mean by "the NVIDIA CPU that was just announced" is Vera. NVIDIA unveiled it at CES as the CPU half of Vera Rubin NVL72, the next-generation AI supercomputer platform, with a launch window of 2H 2026 [4].
Two specs of the Vera CPU itself are confirmed by Tom's Hardware: 88 custom-designed Olympus Arm cores and up to 176 threads of concurrency [5][6]. The clock, TDP, process node, and memory channel layout are all not confirmed inside our verified set.
The accompanying Rubin GPU and system fabric are where the numbers get loud. Vera Rubin's headline marketing line reduces to two claims — 5× greater inference performance and 10× lower cost per token versus Blackwell GB200 [4] — backed by an aggressive jump in NVLink 6 bandwidth.
| Item | Value | Source |
|---|---|---|
| Vera CPU cores | 88 (Olympus Arm) | Tom's [5] |
| Vera threads | up to 176 | Tom's [6] |
| Rubin inference (NVFP4) | 50 PFLOPS | Tom's [4] |
| vs Blackwell GB200 inference | 5× | Tom's [4] |
| Cost per token | 10× lower | Tom's [4] |
| HBM4 memory | 288 GB / 22 TB/s | Tom's [4] |
| NVLink C2C (CPU↔GPU) | 1.8 TB/s (2×) | Tom's [4] |
| NVLink 6 (per-GPU, bi-directional) | 3.6 TB/s | Tom's [4] |
| NVLink 6 switch (each) | 28 TB/s, 9 per rack | Tom's [4] |
| Per-rack scale-up bandwidth | 260 TB/s | Tom's [4] |
| Spectrum-6 networking | 102.4 Tb/s | Tom's [4] |
| Launch window | 2H 2026 | Tom's [4] |
Vera CPU clock, TDP, process, and memory channel count are not confirmed inside the verified source set. Every number in the table comes from Tom's Hardware's "Vera Rubin NVL72" launch story.
The GB10 Superchip is the chip most often described as NVIDIA's closest move toward the consumer PC market — but the framing matters. The DGX Spark system that hosts GB10 shipped on 2025-10-15 [2] and the positioning is not a laptop. It is an "AI workstation you put on your desk", with marketing built around running large models locally.
The most striking number is model scale. A single DGX Spark is described as handling inference of models up to 200 billion parameters, and two units connected together up to 405 billion parameters [1]. That sentence captures GB10's position better than any single spec.
| Item | Value | Source |
|---|---|---|
| CPU cores | Arm-based Grace, 20-core | MediaTek [1] |
| Unified memory | 128 GB | MediaTek [1] |
| AI performance | up to 1 PFLOP | MediaTek [1] |
| Networking | ConnectX-7 built-in | MediaTek [1] |
| Single-node model ceiling | 200 B params | MediaTek [1] |
| Dual-node model ceiling | 405 B params | MediaTek [1] |
| Co-designed by | NVIDIA × MediaTek | MediaTek [1] |
| Release date | 2025-10-15 | MediaTek [2] |
Process node, exact TDP, clocks, and LPDDR5X bandwidth are not confirmed inside our verified sources. MediaTek's press release directly states: "GB10 delivers up to 1 PFLOP of AI performance." [1]
A separate "Windows on ARM consumer laptop SoC from NVIDIA" — the line that has been circulating under codenames like "N1" — is not confirmed as formally launched in the same window by any source we verified.
The data-center foundation is the NVIDIA Grace Superchip. Two 72-core dies are stitched together over NVLink C2C for a total of 144 cores on Arm Neoverse-V2 [3][7]. ServeTheHome's published deep dive lines up the core specs as follows.
| Item | Value | Source |
|---|---|---|
| Core architecture | Arm Neoverse-V2 | STH [7] |
| Total cores | 144 (72 × 2 dies) | STH [3] |
| L1 cache (per core) | 64 KB I + 64 KB D | STH [3] |
| L2 cache (per core) | 1 MB | STH [3] |
| L3 cache (per Superchip) | 234 MB | STH [3] |
| Memory | LPDDR5X · 500 GB/s per CPU | STH [3] |
| PCIe | Gen5, 128 lanes (x16 × 8) | STH [3] |
| NVLINK C2C (socket-to-socket) | 900 GB/s | STH [3] |
| FP64 peak | 7.1 TFLOPS | STH [3] |
| TDP (incl. LPDDR5X) | 500 W | STH [3] |
Grace's distinctive choice is that a data-center CPU adopts LPDDR5X. The 500 GB/s-per-CPU figure sits on a different axis than the typical 12-channel DDR5 server playbook. The production / volume status of follow-on SKUs (GH200 / GB200 / GB300) is not confirmed inside our verified set at SKU-level detail.
This is where the piece has to be most honest. The only AMD/Intel comparison target inside our verified set is the dual-socket AMD EPYC 7763 that ServeTheHome used for the Grace Superchip story [8]. EPYC 7763 is Zen 3 / Milan — not the current EPYC 9005 "Turin" (Zen 5), nor Xeon 6 (6900P / 6700P), Ryzen 9000, Core Ultra 200V/200S, Apple M4, or Snapdragon X Elite / X2. None of those is present in the verified set at per-benchmark numeric resolution.
So this article deliberately does not produce a "who wins which benchmark" verdict. What the verified specs do let us draw is a shape.
The honest take, then, is that the verified set lets us describe what NVIDIA built, but does not let us declare a per-benchmark winner against AMD or Intel current parts. Not hiding that is, in our view, the credible move.
The reason an apples-to-apples comparison with AMD and Intel does not cleanly fall out is that NVIDIA's CPU was not designed to be a standalone CPU. — provisional conclusion
Grounded in the verified facts, NVIDIA's CPU strategy reads in four moves.
1. The point of the CPU is the GPU coupling. Grace-era NVLINK C2C at 900 GB/s [3] and Vera–Rubin's 1.8 TB/s [4] are not just interconnect numbers — they are the core thesis. They raise CPU↔GPU memory coherence and bandwidth to a level that an "x86 + discrete GPU" board cannot reach. The honest comparison target is "EPYC plus an external GPU" rather than "EPYC alone."
2. Resetting the inference-cost curve. Vera Rubin's strongest marketing line is the "5× inference, 10× lower cost per token" pair [4]. That moves the axis of comparison from raw CPU performance to cost per token, an AI-workload-native unit that an x86 SKU table is not naturally shaped to answer.
3. MediaTek as the bridgehead for ARM PC. GB10 is the first release in which MediaTek is named as co-designer [1]. The press release explicitly notes MediaTek's role as a vendor that ships over two billion connected devices a year [1] — the kind of supply, modem, power-management, and platform-IP fabric NVIDIA would need to scale into the consumer ARM PC market. Whether a "Windows on ARM consumer-laptop NVIDIA SoC" itself has a model and a date is not confirmed in our verified set.
4. Extending the CUDA / DGX lock-in. DGX Spark being marketed as a single system that holds 200 B parameters of inference and 405 B across two nodes [1] is strategic: it ensures the first system a developer or researcher physically touches is already inside the CUDA + DGX stack. The product is positioned less as a unique CPU and more as "the smallest DGX you can put on your desk."
The keynote of NVIDIA's GTC Taipei 2026 is scheduled for the day after this piece publishes. According to NVIDIA's official event page, the keynote is 2026-06-01 at 11:00 local time at the Taipei Music Center, with the workshop on 6/2 and conference days 6/3–6/4 [9]. The official page also lists the pre-game show as hosted by Goldman Sachs' Bruce Lu and Gartner's Tracy Tsai [9]. Anything announced at the keynote itself — additional specs, roadmaps, pricing — sits outside this piece's verified set and is not confirmed here; a follow-up is the right place for it.